Hello friends all of you are welcome in this blog. In this blog, 'Electronics devices and circuits' is Raghavkrules. Here you will find all kind of Registers and electronics devices circuit explanations.
An adder is a digital logic circuit in electronics that implements addition of numbers. In many computers and other types of processors, adders are used to calculate addresses, similar operations and table indices in the ALU and also in other parts of the processors. These can be built for many numerical representations like excess-3 or binary coded decimal. The adders are classified into two types -
1. Half adder
2. Full adder
Half adder
The half adder adds two binary digits called as augend and addend and produces two outputs as sum and carry. XOR is applied to both inputs to produce sum and AND gate is applied to both inputs to produce carry.
0+0 = 0 0+1 = 1 1+0 = 1 1+1 = 10
These are the least possible single-bit combinations. But the result for 1+1 is 10, the sum result must be re-written as a 2-bit output. Thus, the equations can be written as 0+0 = 00 0+1 = 01 1+0 = 01 1+1 = 10
The output ‘1’of ‘10’ is carry-out. ‘SUM’ is the normal output and ‘CARRY’ is the carry-out.
From above table it is cleared that 1-bit adder can be easily implemented with the help of the XOR Gate for the output ‘SUM’ and an AND Gate for the ‘Carry’. When we need to add, two 8-bit bytes together, we can be done with the help of a full-adder logic. The half-adder is useful when you want to add one binary digit quantities. A way to develop a two-binary digit adders would be to make a truth table and reduce it. When you want to make a three binary digit adder, do it again. When you decide to make a four digit adder, do it again. The circuits would be fast, but development time is slow.
The simplest expression uses the exclusive OR function as Sum=AÅB. An equivalent expression in terms of the basic AND, OR, and NOT is: SUM=A|.B+A.B’
Full adder
This adder is difficult to implement than a half-adder. The difference between a half-adder and a full-adder is that the full-adder has three inputs and two outputs, whereas half adder has only two inputs and two outputs. The first two inputs are A and B and the third input is an input carry as C-IN. When a full-adder logic is designed, you string eight of them together to create a byte-wide adder and cascade the carry bit from one adder to the next.
The output carry is designated as C-OUT and the normal output is designated as S.
With the truth-table, the full adder logic can be implemented. You can see that the output S is an XOR between the input A and the half-adder, SUM output with B and C-IN inputs. We take C-OUT will only be true if any of the two inputs out of the three are HIGH.
So, we can implement a full adder circuit with the help of two half adder circuits. At first, half adder will be used to add A and B to produce a partial Sum and a second half adder logic can be used to add C-IN to the Sum produced by the first half adder to get the final S output.
Thanks for spending your valuable time with this article, and we hope that you might have received a good content about Adder Please share your views on this topic by commenting below and you can see my video on this topic.
The Uni junction Transistor or UJT
for short, is another solid state three terminal device that can be used
in gate pulse, timing circuits and trigger generator applications to
switch and control either thyristors and triac’s for AC power control
type applications.
Like diodes, uni +junction transistors are constructed from
separate P-type and N-type semiconductor materials forming a single
(hence its name Uni-Junction) PN- junction within the main conducting
N-type channel of the device.
Although the Unijunction Transistor has the name of
a transistor, its switching characteristics are very different from
those of a conventional bipolar or field effect transistor as it can not
be used to amplify a signal but instead is used as a ON-OFF switching
transistor. UJT’s have unidirectional conductivity and negative
impedance characteristics acting more like a variable voltage divider
during breakdown.
Like N-channel FET’s, the UJT consists of a single solid
piece of N-type semiconductor material forming the main current carrying
channel with its two outer connections marked as Base 2 ( B2 ) and Base 1 ( B1 ). The third connection, confusingly marked as the Emitter ( E )
is located along the channel. The emitter terminal is represented by an
arrow pointing from the P-type emitter to the N-type base.
The Emitter junction is positioned along the channel so that it is closer to terminal B2 than B1.
An arrow is used in the UJT symbol which points towards the base
indicating that the Emitter terminal is positive and the silicon bar is
negative material. Below shows the symbol, construction, and equivalent
circuit of the UJT.
Symbol and Construction :
The symbol for the uni junction transistor (N type) looks as shown in beloe fig. it is quite similar to that of
the junction field effect transistor (JFET), except that it has a bent
arrow representing the Emitter( E ) input.
While similar in respect of their ohmic channels.
The N-type channel basically consists of two resistors RB2 and RB1 in series with an equivalent (ideal) diode, D
representing the p-n junction connected to their center point. This
Emitter p-n junction is fixed in position along the ohmic channel during
manufacture.
Resistance RB1 is given between the Emitter, E and terminal B1, while resistance RB2 is given between the Emitter, E and terminal B2. As the physical position of the p-n junction is closer to terminal B2 than B1 the resistive value of RB2 will be less than RB1.
These two series resistances produce a voltage divider
network between the two base terminals of the unijunction transistor and
since this channel stretches from B2 to B1,
when a voltage is applied across the device, the potential at any point
along the channel will be in proportion to its position between
terminals B2 and B1. The level of the voltage gradient therefore depends upon the amount of supply voltage.
When used in a circuit, terminal B1 is connected to ground and the Emitter serves as the input to the device. Suppose a voltage VBB is applied across the UJT between B2 and B1 so that B2 is biased positive relative to B1.
Operation of a UJT :
This transistor operation starts by making the emitter supply voltage
to zero, and its emitter diode is reverse biased with the intrinsic
stand-off voltage. If VB is the voltage of the emitter diode, then the
total reverse bias voltage is VA + VB = Ƞ VBB + VB. For silicon VB = 0.7
V, If VE gets slowly increases to the point where VE = Ƞ VBB, then IE
will be reduced to zero. Therefore, on each side of the diode, equal
voltages results no current flow through it, neither in reverse bias nor
in forward bias.
When the emitter supply voltage is
increased rapidly, then the diode becomes forward-biased and exceeds the
total reverse bias voltage (Ƞ VBB + VB). This emitter voltage value VE
is called the peak-point voltage and is denoted by VP. When VE = VP,
emitter current IE flows through the RB1 to the ground, that is, B1.
This is the minimum current required for triggering the UJT. This is
called the peak-point emitter current and is denoted by IP. Ip is
inversely proportional to the Inter-base voltage, VBB.
Now when the emitter diode starts
conducting, charge carriers are injected into the RB region of the bar.
As the resistance of a semiconductor material depends upon doping, the
resistance of RB decreases due to additional charge carriers.
Then the voltage drop across RB also
decreases, with the decrease in resistance because the emitter diode is
heavily forward biased. This in turn results in larger forward current,
and as a result charge carriers are injected and it will cause the
reduction in the resistance of the RB region. Thus, the emitter current
goes on increasing until the emitter power supply is in limited range.
VA decreases with the increase in
emitter current, and UJT have the negative resistance characteristic.
The base 2 is used for applying external voltage VBB across it. The
terminals E and B1 are the active terminals. UJT usually gets triggered
by applying a positive pulse to the emitter, and it can be turned off by
applying a negative trigger pulse.
Thanks for spending your valuable time with this article, and we hope that you might have received a good content about UJT Please share your views on this topic by commenting below.
When a voltage Vs (supply voltage) is firstly applied, the uni junction transistor is "OFF" and the capacitor C1 is fully discharged but begins to charge up exponentially through resistor R3. As the Emitter of the UJT is connected to the capacitor, when the Vc (charging voltage)
across the capacitor becomes greater than the diode volt drop value,
the p-n junction behaves as a normal diode and becomes forward biased
triggering the UJT into conduction. The UJT is “Turn ON”.
At this point the Emitter to B1 impedance collapses as the Emitter goes
into a low impedance saturated state with the flow of Emitter current
through R1 taking place.
As the ohmic value of resistor R1 is very low, the capacitor discharges rapidly through the UJT and a fast rising voltage pulse appears across R1. Also, because the capacitor discharges more quickly through the UJT than it does charging up through resistor R3, the discharging time is a lot less than the charging time as the capacitor discharges through the low resistance UJT.
When the voltage across the capacitor decreases below the holding point of the p-n junction ( VOFF ), the UJT turns “OFF” and no current flows into the Emitter junction so once again the capacitor charges up through resistor R3 and this charging and discharging process is constantly repeated while there is a supply voltage, Vs applied.
UJT Oscillator Waveforms :
The relaxation oscillator continually
switches "ON" and "OFF" without any feedback. The frequency of operation
of the oscillator is directly affected by the value of the charging
resistance R3, in series with the capacitor C1 and the value of η. The output pulse shape generated from the Base1 (B1)
terminal is that of a sawtooth waveform and to regulate the time
period, you only have to change the ohmic value of resistance, R3 since it sets the RC time constant for charging the capacitor.
The time period, T of the
sawtoothed waveform will be given as the charging time plus the
discharging time of the capacitor. As the discharge time, τ1 is generally very short in comparison to the larger RC charging time, τ2 the time period of oscillation is more or less equivalent to T ≅ τ2. The frequency of oscillation is therefore given by ƒ = 1/T
Thanks for spending your valuable time with this article, and we hope
that you might have received a good content about UJT Please share your
views on this topic by commenting below.
